Publications

Reducing Spiking Neural Network Inference Latency for Behavior Cloning with Input Adaptive Leakage

Takehiro Habara, Takashi Sato, and Hiromitsu Awano

Scientific Reports, 2026accepted

Leak-CIM: A PVT-Robust and Energy-Efficient SRAM Computing-in-Memory Macro Exploiting Transistor Leakage

Hiroto Tagata, Takashi Sato, and Hiromitsu Awano

IEEE Transactions on Very Large Scale Integration Systems, 2026accepted

Frieren: a Fault-Tolerant Reconfigurable Energy-Efficient Computing Architecture with Enhanced Reliability in Harsh Environments

Quan Cheng, Qiufeng Li, Weirong Dong, Mingtao Zhang, Ruilin Zhang, Mingqiang Huang, Hao Yu, Yiyu Shi, Hiromitsu Awano, Takashi Sato, Mehdi Saligane, Longyang Lin, and Masanori Hashimoto

IEEE Transactions on Computers, 2026acceptedDOI

Raisu: A Radiation-Tolerant Neuromorphic Imager With In-Pixel Self-Healing and Unified Spiking Processing for Spaceborne Vision

Quan Cheng, Qiufeng Li, Zhengke Yang, Zhen Kong, Gaoqiang Niu, Yuan Liang, Jiamin Li, Jeong Hoan Park, Wang Liao, Hiromitsu Awano, Takashi Sato, Longyang Lin, and Masanori Hashimoto

IEEE Journal of Solid-State Circuits, 2026DOI

Biologically Constrained DNA Encoding with Triplet Networks for Similarity Image Retrieval

Takefumi Koike, Hiromitsu Awano, and Takashi Sato

IEEE Transactions on Computational Biology and Bioinformatics, pp. 1–13, 2026DOI

Beamforming Feedback-Based Respiration and Heart Rate Estimation Toward Firmware-Agnostic WiFi Sensing

T. Kanda, S. Kondo, H. Shimomura, Takashi Sato, Hiromitsu Awano, and K. Yamamoto

IEEE Access, vol. 13, pp. 146008–146019, 2025DOI

Analog In-Memory Computing from a Memory-Agnostic Perspective: Theory, Nonidealities, and Hardware-Aware Training

Yusuke Sakemi, Hiromitsu Awano, and Takashi Morie

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2025DOI

Online Training and Inference System on Edge FPGA Using Delayed Feedback Reservoir

Sosei Ikeda, Hiromitsu Awano, and Takashi Sato

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 44, pp. 3323–3335, 2025

A Robust and Energy Efficient Hyperdimensional Computing System for Voltage-scaled Circuits

Dehua Liang, Hiromitsu Awano, Noriyuki Miura, and Jun Shiomi

ACM Transactions on Embedded Computing Systems, vol. 23, no. 6, pp. 1–20, 2024

BayesianSpikeFusion: Accelerating Spiking Neural Network Inference via Bayesian Fusion of Early Prediction

Takehiro Habara, Takashi Sato, and Hiromitsu Awano

Frontiers in Neuroscience, vol. 18, 2024DOI

StrideHD: A Binary Hyperdimensional Computing System Utilizing Window Striding for Image Classification

Dehua Liang, Jun Shiomi, Noriyuki Miura, and Hiromitsu Awano

IEEE Open Journal of Circuits and Systems, vol. 5, pp. 211–223, 2024

Double MAC on a Cell: A 22-nm 8T-SRAM based Analog In-Memory Accelerator for Binary/Ternary Neural Networks Featuring Split Wordline

Hiroto Tagata, Takashi Sato, and Hiromitsu Awano

IEEE Open Journal of Circuits and Systems, vol. 5, pp. 328–340, 2024

Uncertainty-aware Haptic Shared Control with Humanoid Robots for Flexible Object Manipulation

Takumi Hara, Takashi Sato, Tetsuya Ogata, and Hiromitsu Awano

IEEE Robotics and Automation Letters, vol. 8, pp. 6435–6442, 2023

Modular DFR: Digital delayed feedback reservoir model for enhancing design flexibility

Sosei Ikeda, Hiromitsu Awano, and Takashi Sato

ACM Transactions on Embedded Computing Systems, vol. 22, no. 5s, pp. 1–20, 2023

Pay Attention via Quantization: Enhancing Explainability of Neural Networks via Quantized Activation

Yuma Tashiro and Hiromitsu Awano

IEEE Access, 2023DOI

B2N2: Resource Efficient Bayesian Neural Network Accelerator Using Bernoulli Sampler on FPGA

Hiromitsu Awano and Masanori Hashimoto

Integration, vol. 89, pp. 1–8, 2023

Hardware-Friendly Delayed-Feedback Reservoir for Multivariate Time-Series Classification

Sosei Ikeda, Hiromitsu Awano, and Takashi Sato

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 11, pp. 3650–3660, 2022

BayesianPUFNet: Training Sample Efficient Modeling Attack for Physically Unclonable Functions

Hiromitsu Awano and Makoto Ikeda

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2022DOI

A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter

Dehua Liang, Jun Shiomi, Noriyuki Miura, Masanori Hashimoto, and Hiromitsu Awano

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E105-D, no. 7, pp. 1273–1282, 2022

Temporal Ensemble SSDLite: Exploiting Temporal Correlation in Video for Accurate Object Detection

Lukas Nakamura and Hiromitsu Awano

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E105-A, no. 7, pp. 1082–1090, 2022

Visualization of chorus structure in multiple frog species by a sound discrimination device

Hiromitsu Awano, Masahiro Shirasaka, Takeshi Mizumoto, Hiroshi G. Okuno, and Ikkyu Aihara

Journal of Comparative Physiology A, vol. 207, no. 1, pp. 87–98, 2021

Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge–Response pair acquisition using Built-In Self-Test before shipping

Yasuhiro Ogasahara, Yohei Hori, Toshihiro Katashita, Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda, and Hanpei Koike

Integration, vol. 71, pp. 144–153, 2020

An ASIC Crypto Processor for 254-bit Prime-Field Pairing Featuring Programmable Arithmetic Core Optimized for Quadratic Extension Field

Hiromitsu Awano, Tadayuki Ichihashi, and Makoto Ikeda

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E102-A, no. 1, pp. 56–64, 2019

Low Latency 256-bit Fp ECDSA Signature Generation Crypto Processor

Shotaro Sugiyama, Hiromitsu Awano, and Makoto Ikeda

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E101-A, no. 12, pp. 2290–2296, 2018

Efficient Aging-Aware Failure Probability Estimation Using Augmented Reliability and Subset Simulation

Hiromitsu Awano and Takashi Sato

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E100-A, no. 12, pp. 2807–2815, 2017

RTN in Scaled Transistors for On-chip Random Seed Generation

Abinash Mohanty, Ketul Sutaria, Hiromitsu Awano, Takashi Sato, and Yu Cao

IEEE Transactions on Very Large Scale Integration Systems, vol. 25, no. 8, pp. 2248–2257, 2017

Scalable Device Array for Statistical Characterization of BTI-Related Parameters

Hiromitsu Awano, Shumpei Morita, and Takashi Sato

IEEE Transactions on Very Large Scale Integration Systems, vol. 25, no. 4, pp. 1455–1466, 2017

A Swarm of Sound-to-Light Conversion Devices for Monitoring Acoustic Communication among Small Nocturnal Animals

Takeshi Mizumoto, Ikkyu Aihara, Takuma Otsuka, Hiromitsu Awano, and Hiroshi G. Okuno

Journal of Robotics and Mechatronics, vol. 29, no. 1, pp. 255–267, 2017

Visualizing Phonotactic Behavior of Female Frogs in Darkness

Ikkyu Aihara, Phillip Bishop, Michel Ohmer, Hiromitsu Awano, Takeshi Mizumoto, Hiroshi Okuno, Peter Narins, and Jean-Marc Hero

Scientific Reports, vol. 7, pp. 10539, 2017

Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter based Importance Sampling

Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E99-A, no. 7, pp. 1390–1399, 2016

Automation of Model Parameter Estimation for Random Telegraph Noise

Hirofumi Shimizu, Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 12, pp. 2383–2392, 2014

BTIarray: A Time-overlapping Transistor Array for Efficient Statistical Characterization of Bias Temperature Instability

Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato

IEEE Transactions on Device and Materials Reliability, vol. 14, no. 3, pp. 833–843, 2014

Spatio-Temporal Dynamics in Collective Frog Choruses Examined by Mathematical Modeling and Field Observation

Ikkyu Aihara, Takeshi Mizumoto, Takuma Otsuka, Hiromitsu Awano, Kohei Nagira, Hiroshi G. Okuno, and Kazuyuki Aihara

Scientific Reports, vol. 4, pp. 3891, 2014

Compact Modeling of Statistical BTI Under Trapping/detrapping

Jyothi Bhaskarr Velamala, Ketul B. Sutaria, Hirofumi Shimizu, Hiromitsu Awano, Takashi Sato, Gilson Wirth, and Yu Cao

IEEE Transactions on Electron Devices, vol. 60, no. 11, pp. 3645–3654, 2013

Bayesian Estimation of Multi-trap RTN Parameters using Markov Chain Monte Carlo Method

Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E95-A, no. 12, pp. 2272–2283, 2012

Improving Robustness of Leakage-Based MOSFET Reservoir Computing Using Adaptive Pulse-Width Control

Ryuto Seki, Masami Utsunomiya, Yu-Guang Chen, Hiromitsu Awano, and Takashi Sato

International Conference on Microelectronic Test Structure, pp. 1–6, 2026DOI

PALETTE: A Reconfigurable LUT-CIM Macro Featuring On-Chip Parallel LUT Update and Pipelined Accumulation

Hiroto Tagata, Takashi Sato, and Hiromitsu Awano

International Conference on Computer-Aided Design, 2026accepted

SOME: Symmetric One-Hot Matching Elector – A Lightweight Microsecond Decoder for Quantum Error Correction

Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Hiromitsu Awano, Shinji Kimura, and Takashi Sato

International Conference on Computer-Aided Design, pp. 1–9, 2025DOI

Window Function-Less DFT with Reduced Noise and Latency for Real-Time Music Analysis

Cai Biesinger, Hiromitsu Awano, and Masanori Hashimoto

European Signal Processing Conference, pp. 431–435, 2025DOI

Zero-Aware Regularization for Energy-Efficient Inference on Akida Neuromorphic Processor

Takehiro Habara, Takashi Sato, and Hiromitsu Awano

IEEE International Symposium on Circuits and Systems, pp. 1–5, 2025DOI

GaitCloud: Leveraging Spatial-Temporal Information for LiDAR-Based Gait Recognition with a True-3D Gait Representation

Shaoxiong Zhang, Hiromitsu Awano, and Takashi Sato

IEEE/CVF Winter Conference on Applications of Computer Vision, pp. 2849–2858, 2025DOI

Random Telegraph Noise Observed on 65-nm Bulk pMOS Transistors at 3.8K

Takuma Kawakami, Takashi Sato, and Hiromitsu Awano

Asia and South Pacific Design Automation Conference, pp. 1438–1443, 2025

A Radiation-Hardened Neuromorphic Imager with Self-Healing Spiking Pixels and Unified Spiking Neural Network for Space Robotics

Quan Cheng, Qiufeng Li, Zhengke Yang, Zhen Kong, Gaoqiang Niu, Yuan Liang, Jiamin Li, Jeong Hoan Park, Wang Liao, Hiromitsu Awano, Takashi Sato, Longyang Lin, and Masanori Hashimoto

Digest of Symposium on VLSI Technology and Circuits, pp. 1–3, 2025DOI

Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline Accumulation

Hiroto Tagata, Takashi Sato, and Hiromitsu Awano

Design Automation Conference, pp. 1–7, 2025DOI

Weighted Range-Constrained Ising-Model Decoder for Quantum Error Correction

Xinyi Guo, Hiromitsu Awano, and Takashi Sato

Design Automation Conference, pp. 1–7, 2025DOI

A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-On-Chip Towards In-Orbit Computing

Q. Cheng, Q. Li, W. Dong, M. Zhang, R. Zhang, M. Huang, H. Yu, Y. Shi, H. Awano, T. Sato, L. Lin, and M. Hashimoto

Proceedings of IEEE Custom Integrated Circuits Conference, pp. 1–3, 2025DOI

S3M: Static Semi-Segmented Multipliers for Energy-efficient DNN Inference Accelerators

Mingtao Zhang, Quan Cheng, Hiromitsu Awano, Longyang Lin, and Masanori Hashimoto

IEEE International Conference on Computer Design, pp. 16–23, 2024

Exploring Surface Code Decoding via Cryo-CMOS for Fault-Tolerant Quantum Computers

Ruotai Wang, Takashi Sato, and Hiromitsu Awano

IEEE International Conference on Quantum Computing and Engineering, pp. 438–439, 2024DOI

Square-Wave Defined Pulse Generator for High Fidelity Gate Operation of Superconducting Qubits

Ryosuke Matsuo, Kazuhisa Ogawa, Hidehisa Shiomi, Makoto Negoro, Ryutaro Ohira, Takefumi Miyoshi, Michihiro Shintani, Hiromitsu Awano, Takashi Sato, and Jun Shiomi

IEEE International Conference on Quantum Computing and Engineering, pp. 378–379, 2024DOI

Triplet network-based DNA encoding for enhanced similarity image retrieval

Takefumi Koike, Hiromitsu Awano, and Takashi Sato

Design Automation Conference, San Francisco, 2024

DNA-Based Similar Image Retrieval via Triplet Network-Driven Encoder

Takefumi Koike, Hiromitsu Awano, and Takashi Sato

Design, Automation, and Test in Europe, pp. 1–2, 2024DOI

Fast Parameter Optimization of Delayed Feedback Reservoir with Backpropagation and Gradient Descent

Sosei Ikeda, Hiromitsu Awano, and Takashi Sato

Design, Automation, and Test in Europe, pp. 1–6, Valencia, Spain, 2024DOI

DependableHD: A Hyperdimensional Learning Framework for Edge-oriented Voltage-scaled Circuits

Dehua Liang, Hiromitsu Awano, Noriyuki Miura, and Jun Shiomi

Asia and South Pacific Design Automation Conference, pp. 416–422, 2023

Introducing Transfer Learning Framework on Device Modeling by Machine Learning

Kota Niiyama, Hiromitsu Awano, and Takashi Sato

International Conference on Microelectronic Test Structure, pp. 1–6, Tokyo, Japan, 2023DOI

Pay Attention via Binarization: Enhancing Explainability of Neural Networks via Binarization of Activation

Yuma Tashiro and Hiromitsu Awano

IEEE International Symposium on Circuits and Systems, pp. 3160–3164, Austin, TX, 2022DOI

DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification

Dehua Liang, Jun Shiomi, Noriyuki Miura, and Hiromitsu Awano

Asia and South Pacific Design Automation Conference, pp. 43–49, 2022Best Paper CandidateDOI

Respiratory Rate Estimation Based on WiFi Frame Capture

Takamochi Kanda, Takashi Sato, Hiromitsu Awano, Sota Kondo, and Koji Yamamoto

IEEE Consumer Communications and Networking Conference, pp. 881–884, 2022DOI

BloomCA: A Memory Efficient Reservoir Computing Hardware Implementation Using Cellular Automata and Ensemble Bloom Filter

Dehua Liang, Masanori Hashimoto, and Hiromitsu Awano

Design, Automation, and Test in Europe, pp. 587–590, 2021

Binary Neural Network in Robotic Manipulation: Flexible Object Manipulation for Humanoid Robot Using Partially Binarized Auto-Encoder on FPGA

Satoshi Ohara, Tetsuya Ogata, and Hiromitsu Awano

International Conference on Intelligent Robots and Systems, pp. 6010–6015, 2021Best RoboCup Paper Award CandidateDOI

BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA

Hiromitsu Awano and Masanori Hashimoto

Design, Automation, and Test in Europe, Grenoble, France, 2020Oral, acceptance rate 26%

33us, 94uJ Optimal Ate Pairing Engine on BN Curve over 254b Prime Field in 65nm CMOS FDSOI

Makoto Ikeda, Tadayuki Ichihashi, and Hiromitsu Awano

Asian Solid-State Circuits Conference, pp. 263–266, 2019DOI

High-Speed ASIC Implementation of Paillier Cryptosystem with Homomorphism

Chun Cai, Hiromitsu Awano, and Makoto Ikeda

IEEE International Conference on ASIC, pp. 1–4, 2019DOI

PUFNet: a Deep Neural Network Based Modeling Attack for Physically Unclonable Function

Hiromitsu Awano, Tomoki Iizuka, and Makoto Ikeda

IEEE International Symposium on Circuits and Systems, Sapporo, Japan, 2019

FourQ on ASIC: Breaking Speed Records for Elliptic Curve Scalar Multiplication

Hiromitsu Awano and Makoto Ikeda

Design, Automation, and Test in Europe, Florence, Italy, 2019Long presentation, acceptance rate 24%

31.3us/Signature-Generation 256-bit Fp ECDSA Cryptoprocessor

Shotaro Sugiyama, Hiromitsu Awano, and Makoto Ikeda

Asian Solid-State Circuits Conference, pp. 153–156, Tainan, Taiwan, 2018

An Encryption-Authentication Unified A/D Conversion Scheme for IoT Sensor Node

Vinod V. Gadde, Hiromitsu Awano, and Makoto Ikeda

Asian Solid-State Circuits Conference, pp. 123–126, Tainan, Taiwan, 2018

ASIC Coprocessor for 254-bit Prime-Field Pairing based on General Purpose Arithmetic Unit on Quadratic Extension Field

Hiromitsu Awano and Makoto Ikeda

International Conference on Advanced Technologies for Communications, Ho Chi Minh, Vietnam, 2018

Ising-PUF: A Machine Learning Attack Resistant PUF Featuring Lattice Like Arrangement of Arbiter-PUFs

Hiromitsu Awano and Takashi Sato

Design, Automation, and Test in Europe, pp. 1447–1452, Dresden, Germany, 2018Oral, acceptance rate 23.7%

Yield Enhancement by Repair Circuits for Ultra-Fine Pitch Stacked-Chip Connection

Keitaro Koga, Hiromitsu Awano, and Makoto Ikeda

Asian Test Symposium, pp. 201–205, Taipei, Taiwan, 2017

Efficient Circuit Failure Probability Calculation along Product Lifetime Considering Device Aging

Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato

Asia and South Pacific Design Automation Conference, pp. 93–98, Chiba, Japan, 2017Acceptance rate 31%

Efficient Transistor-level Timing Yield Estimation via Line Sampling

Hiromitsu Awano and Takashi Sato

Design Automation Conference, Austin, TX, 2016Acceptance rate 22.6%

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation

Song Bian, Michihiro Shintani, Shumpei Morita, Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato

Great Lakes Symposium on VLSI, pp. 203–208, Boston, MA, 2016

Physically Unclonable Function Using RTN-Induced Delay Fluctuation in Ring Oscillators

Motoki Yoshinaga, Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato

IEEE International Symposium on Circuits and Systems, pp. 2619–2622, Montreal, Canada, 2016

Efficient Transistor-level Timing Yield Estimation via Line Sampling

Hiromitsu Awano and Takashi Sato

ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Santa Rosa, CA, 2016

Fast Monte Carlo for Timing Yield Estimation via Line Sampling

Hiromitsu Awano and Takashi Sato

Workshop on Variability Modeling and Characterization, Austin, TX, 2015

ECRIPSE: An Efficient Method for Calculating RTN-Induced Failure Probability of an SRAM Cell

Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato

Design, Automation, and Test in Europe, pp. 549–554, Grenoble, France, 2015Oral, acceptance rate 22.4%

Recognition of In-field Frog Chorusing using Bayesian Nonparametric Microphone Array Processing

Yoshiaki Bando, Takuma Otsuka, Ikkyu Aihara, Hiromitsu Awano, Katsutoshi Itoyama, Kazuyoshi Yoshii, and Hiroshi G. Okuno

AAAI Workshop on Computational Sustainability, Austin, TX, 2015

A Scalable Device Array for Statistical Device-Aging Characterization (invited)

Takashi Sato, Hiromitsu Awano, and Masayuki Hiromoto

IEEE International Conference on Solid-State and Integrated Circuit Technology, pp. 255–258, Guilin, China, 2014

Variability in Device Degradations: Statistical Observation of NBTI for 3996 Transistors

Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato

European Solid-State Device Research Conference, pp. 218–221, Venice, Italy, 2014

Statistical Observation of NBTI and PBTI Degradations

Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato

Workshop on Variability Modeling and Characterization, San Jose, CA, 2013

Logarithmic Modeling of BTI under Dynamic Circuit Operation: Static, Dynamic and Long-Term Prediction

Jyothi Bhaskarr Velamala, Ketul B. Sutaria, Hirofumi Shimizu, Hiromitsu Awano, Takashi Sato, Gilson Wirth, and Yu Cao

IEEE International Reliability Physics Symposium, pp. CM.3.1–CM.3.5, 2013DOI

Multi-trap RTN Parameter Extraction based on Bayesian Inference

Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato

International Symposium on Quality Electrical Design, pp. 597–602, Santa Clara, CA, 2013

Statistical Aging Under Dynamic Voltage Scaling: a Logarithmic Model Approach

Jyothi Bhaskarr Velamala, Ketul B. Sutaria, Hirofumi Shimizu, Hiromitsu Awano, Takashi Sato, and Yu Cao

IEEE Custom Integrated Circuits Conference, pp. 6.3.1–6.3.4, San Jose, CA, 2012

Statistical Observations of NBTI-Induced Threshold Voltage Shifts on Small Channel-Area Devices

Takashi Sato, Hiromitsu Awano, Hirofumi Shimizu, Hiroshi Tsutsui, and Hiroyuki Ochi

International Symposium on Quality Electrical Design, pp. 306–311, Santa Clara, CA, 2012

Use of a Sparse Structure to Improve Learning Performance of Recurrent Neural Networks

Hiromitsu Awano, Shun Nishide, Hiroaki Arie, June Tani, Hiroshi G. Okuno, and Tetsuya Ogata

International Conference on Neural Information Processing, pp. 323–331, Shanghai, 2011DOI

Human-Robot Cooperation in Arrangement of Objects Using Confidence Measure of Neuro-dynamical Systems

Hiromitsu Awano, Tetsuya Ogata, Shun Nishide, Toru Takahashi, Kazunori Komatani, and Hiroshi G. Okuno

International Conference on Systems, Man, and Cybernetics, pp. 2533–2538, 2010

AIチップ入門：機械学習のためのハードウェアアクセラレーション

粟野 皓光

コンピュータビジョンとイメージメディア研究会（招待講演）, 2025

ベイジアン深層ニューラルネットのハードウェアアクセラレーション

粟野 皓光

回路とシステムワークショップ A分科会（招待講演）, 2020

Security Evaluation of Physically Unclonable Function in Deep Learning Era

Hiromitsu Awano

The 8th Korea-Japan Joint Workshop on Complex Communication Sciences, Hiroshima, Japan, 2020

Physically Unclonable Functionとモデリング攻撃

粟野 皓光

東北支部講演会（招待講演）, 2019

オープンソース機械学習ライブラリを用いたPUFに対するモデリング攻撃

粟野 皓光

第2回PUF技術シンポジウム，立命館大学東京キャンパス, 2019

Line samplingを用いたモンテカルロ法に基づくタイミング歩留り解析の高速化

粟野 皓光 and 佐藤 高史

VLSI設計技術研究会 VLD2016-117（招待講演）, 2017

モンテカルロ法と集積回路設計の接点

粟野 皓光

IPSJ-ONE 2017（招待講演）, 2017

ニューロモーフィックチップAkidaにおける高電力効率な推論のためのゼロアウェアなSNN学習法

羽原 丈博, 佐藤 高史, and 粟野 皓光

情報処理学会DAシンポジウム2024, 2024

誤り耐性量子コンピュータの実現に向けた表面符号デコーダの極低温CMOS集積回路による実装検討

王 若泰, 佐藤 高史, and 粟野 皓光

情報処理学会DAシンポジウム2024, 2024

4.2Kでの65nmバルクpMOSトランジスタにおけるランダムテレグラフノイズの評価

川上 拓真, 佐藤 高史, and 粟野 皓光

情報処理学会DAシンポジウム2024, 2024

ダイナミック比較器とLookup Tableを用いた乗算不要な機械学習向けインメモリアクセラレータ

田形 寛斗, 佐藤 高史, and 粟野 皓光

LSIとシステムワークショップ2024, 2024

エッジデバイス実装を指向したロボット遠隔操作時のハプティックガイダンス生成法の検討

原 拓己, 佐藤 高史, and 粟野 皓光

ロボティクス・メカトロニクス講演会2024, 2024

リーク電流で演算する量子化ニューラルネットワーク向け低電力SRAMインメモリアクセラレータ

田形 寛斗, 佐藤 高史, and 粟野 皓光

情報処理学会DAシンポジウム2023, 2023

ヘブ則に基づく動的重み調整手法を利用したスパイキングニューラルネットワークの低レイテンシ・低消費エネルギ推論

羽原 丈博, 佐藤 高史, and 粟野 皓光

情報処理学会DAシンポジウム2023, 2023

適応的閾値制御に基づくスパイキングニューラルネットワークの推論エネルギー削減

羽原 丈博, 佐藤 高史, and 粟野 皓光

情報処理学会DAシンポジウム2022, 2022

8T-SRAMを用いた同時２入力対応な２値化ニューラルネットワーク用インメモリアクセラレータ

田形 寛斗, 佐藤 高史, and 粟野 皓光

情報処理学会DAシンポジウム2022, 2022

離散化アテンションによる説明可能な自動操舵システム

田代 悠馬 and 粟野 皓光

情報処理学会DAシンポジウム2022, 2022

スパイキングニューラルネットワークの高速低エネルギー推論に向けた動的閾値調整手法

羽原 丈博 and 粟野 皓光

電子情報通信学会VLD設計技術研究会, 2022

8T-SRAMを用いた高スループットな2値化ニューラルネットワーク用インメモリアクセラレータ

田形 寛斗 and 粟野 皓光

電子情報通信学会VLD設計技術研究会, 2022

遠隔ロボットによる円滑な柔軟物操作のための力触覚ガイドつき制御システム

飯田 智子 and 粟野 皓光

電子情報通信学会VLD設計技術研究会, 2022

FPGA実装を指向した部分2値化オートエンコーダに基づく人型ロボットによる柔軟物操作システム

大原 慧, 尾形 哲也, and 粟野 皓光

情報処理学会DAシンポジウム2021, 2021

MOSFETリザバーと線形出力層を用いた短時間学習

村田 寛也, 久米 祐貴, 辺 松, 粟野 皓光, and 佐藤 高史

情報処理学会DAシンポジウム2021, 2021

ビット重要度の違いに着目した符号アテンションによる説明能力向上

田代 悠馬 and 粟野 皓光

情報処理学会DAシンポジウム2021, 2021

ベイジアンフュージョンによるスパイキングニューラルネットワークの低エネルギ推論

赤木 勇統 and 粟野 皓光

情報処理学会DAシンポジウム2021, 2021

2値化オートエンコーダを用いたヒューマノイドロボットによる柔軟物操作のための軽量End-to-End学習

大原 慧, 尾形 哲也, and 粟野 皓光

情報処理学会第82回全国大会, 2020

高位設計フローにベイズ最適化法を応用した設計空間探索

中山 亮平, 粟野 皓光, and 池田 誠

電子情報通信学会ハードウェアセキュリティ研究会, 2019

深層学習を利用したPUFに対する攻撃耐性の評価

粟野 皓光, 飯塚 知希, and 池田 誠

電子情報通信学会総合大会企画セッション, 2019

PUFを用いた個体識別システムにおける機械学習攻撃に対する脆弱性の評価

飯塚 知希, 小笠原 泰弘, 片下 敏宏, 堀 洋平, 粟野 皓光, and 池田 誠

電子情報通信学会ハードウェアセキュリティ研究会, 2019

Micciancio-Walterアルゴリズムを用いた高速なガウシアンサンプラーの設計

古賀 啓太郎, 粟野 皓光, and 池田 誠

電子情報通信学会ハードウェアセキュリティ研究会, 2019

超高速な楕円曲線暗号の実現に向けたFourQのASIC実装

粟野 皓光 and 池田 誠

LSIとシステムワークショップ, 2018

65nmプロセスを用いたOptimal Ateペアリング向け12次拡大体演算器の評価

市橋 忠之, 粟野 皓光, and 池田 誠

電子情報通信学会ハードウェアセキュリティ研究会, 2018

楕円曲線デジタル署名アルゴリズムの高速ハードウェア設計

杉山 昇太郎, 粟野 皓光, and 池田 誠

電子情報通信学会ハードウェアセキュリティ研究会, 2018

深層ニューラルネットワークを用いたDouble-Arbiter PUFに対するモデリング攻撃

飯塚 知希, 粟野 皓光, and 池田 誠

電子情報通信学会VLD設計技術研究会, 2018

2次拡大体上の汎用演算器を用いた254bit素数ペアリング向けASICコプロセッサ

粟野 皓光, 市橋 忠之, and 池田 誠

暗号と情報セキュリティシンポジウム, 2018

ツイストしたエドワーズ曲線上のスカラー倍算のハードウェア実装

杉山 昇太郎, 粟野 皓光, and 池田 誠

暗号と情報セキュリティシンポジウム, 2018

BN曲線上におけるOptimal Ateペアリング向け演算ハードウェアの最適化

市橋 忠之, 粟野 皓光, and 池田 誠

電子情報通信学会技術報告会（デザインガイア2017）, 2017

チャレンジヒステリシス特性を有するPUFの設計とシミュレーションに基づく性能評価

粟野 皓光 and 佐藤 高史

情報処理学会DAシンポジウム2017, pp. 79–84, 2017

信号確率伝播に基づいたプロセッサのためのNBTI起因最大遅延パスの抽出

辺 松, 新谷 道広, 森田 俊平, 粟野 皓光, 廣本 正之, and 佐藤 高史

第29回回路とシステムワークショップ, pp. 30–35, 2016

モンテカルロ法に基づくタイミング歩留り解析の高速化

粟野 皓光 and 佐藤 高史

電子情報通信学会技術報告会（デザインガイア2015）, 2015

デバイス特性の経年劣化に起因する不良確率変化の効率的な解析手法

粟野 皓光, 廣本 正之, and 佐藤 高史

情報処理学会DAシンポジウム2015, pp. 169–174, 2015

視聴覚統合NMFによるカエル合唱音声の分析

糸山 克寿, 坂東 宜昭, 粟野 皓光, 合原 一究, and 吉井 和佳

情報処理学会研究報告 音楽情報科学, vol. 2015-MUS-107, no. 55, pp. 1–6, 2015

RTN起因のリングオシレータ発振周波数変動を利用したPUF

吉永 幹, 粟野 皓光, 廣本 正之, and 佐藤 高史

電子情報通信学会VLSI設計技術研究会, 2015

NBTIによる閾値電圧変化の確率的モデル化に関する一考察

佐藤 雅紘, 飯塚 翔一, 粟野 皓光, 橋本 昌宜, and 尾上 孝雄

電子情報通信学会総合大会, 2015

RTNを考慮したSRAM不良確率の高速計算

粟野 皓光, 廣本 正之, and 佐藤 高史

電子情報通信学会技術研究報告（デザインガイア2014）, 2014

ランダムテレグラフノイズを用いたチップ識別手法の一検討

吉永 幹, 粟野 皓光, 廣本 正之, and 佐藤 高史

電子情報通信学会ソサイエティ大会, 2014

3996トランジスタにおけるNBTI劣化の統計的ばらつき

粟野 皓光, 廣本 正之, and 佐藤 高史

情報処理学会DAシンポジウム2014, pp. 3–8, 2014

振動子モデルと音声可視化システムを用いたアマガエルの合唱法則の解析

合原 一究, 粟野 皓光, 水本 武志, 坂東 宜昭, 大塚 琢馬, 柳楽 浩平, and 奥乃 博

第39回AIチャレンジ研究会，人工知能学会, 2014

トランジスタアレイを用いたBTI劣化の統計的観測

粟野 皓光 and 佐藤 高史

情報処理学会DAシンポジウム2013, pp. 85–90, 2013

情報量規準を用いるRTNモデルパラメータ推定の自動化

清水 裕史, 粟野 皓光, 筒井 弘, 越智 裕之, and 佐藤 高史

情報処理学会DAシンポジウム2012, 2012

ランダムテレグラフノイズモデル化のためのパラメータ推定法の検討

粟野 皓光, 清水 裕史, 筒井 弘, 越智 裕之, and 佐藤 高史

電子情報通信学会技術研究報告（デザインガイア2011）, 2011

再帰結合神経回路モデルへのスパース構造導入による学習能力の向上

粟野 皓光, 尾形 哲也, 谷 淳, 高橋 徹, and 奥乃 博

情報処理学会第73回全国大会, 2011

確信度を用いた物体配置作業における人間ロボット協調

粟野 皓光, 尾形 哲也, 高橋 徹, 駒谷 和範, and 奥乃 博

日本ロボット学会第28回学術講演会, 2010

RNNを用いた行為予測による人間とロボットの協調物体配置

粟野 皓光, 尾形 哲也, 高橋 徹, 駒谷 和範, and 奥乃 博

情報処理学会第72回全国大会, 2010