Research

We pursue "embodied computational intelligence" by integrating three axes: LSI design, robotics, and computing. Our research spans the full stack — from circuits and learning algorithms to real-world robots.

01

AI for Circuits

Automating IC design with LLMs

Conventional IC design has required expert designers to spend enormous time writing HDL code and running verification. Our lab introduces large language models (LLMs) into the circuit design process, building a new EDA flow that automates everything from natural-language specification to Verilog code generation and layout design (GDSII generation).

• Generative AI for EDA
• LLM
• Auto Synthesis

Current topics

• Custom layout generation with a general-purpose LLM agent: like a human designer, the LLM repeatedly edits the Python script that emits GDS while checking DRC/LVS results (validated on SkyWater 130 nm with an OPAMP, standard cells and an SRAM bitcell, 2026)
• LLM agents that generate Verilog from natural-language specifications and close the loop with simulation-based verification (in progress)
• Machine-learning-based device modeling with transfer learning (ICMTS 2023) and Bayesian-optimization-driven design-space exploration for high-level synthesis

02

Circuits for AI

High-efficiency edge AI accelerators

As AI models such as Transformers and diffusion models grow in size, general-purpose CPUs and GPUs become bottlenecks in power and throughput. We research domain-specific architectures that execute specific AI algorithms with maximum efficiency.

• Domain-Specific Architecture
• FPGA / ASIC
• Low-Power VLSI

Current topics

• SRAM compute-in-memory: Leak-CIM computes with transistor leakage current, PALETTE is a reconfigurable LUT-based CIM, and an 8T-SRAM analog CIM; all fabricated and measured in 22 nm (IEEE TVLSI 2026, ICCAD 2026, IEEE OJCAS 2024)
• Multiplication-free, LUT-based all-digital DNN accelerator (DAC 2025)
• Low-latency, low-energy inference for spiking neural networks (SNNs): early prediction, adaptive thresholds, and measurements on the commercial neuromorphic chip Akida (Frontiers in Neuroscience 2024, ISCAS 2025, Scientific Reports 2026)
• On-chip online training with reservoir computing and Bayesian neural networks with uncertainty estimation on FPGAs (IEEE TCAD 2025, DATE 2020)
• Hyperdimensional computing and explainability through quantization/binarization (IEEE OJCAS 2024, IEEE Access 2023)

03

Systems & Robotics

Robotic applications of our own chips

We deploy AI chips and circuit design methods developed in the lab onto real intelligent robots. By running LLM-based imitation learning and complex trajectory generation in real time on our own hardware (FPGAs and in-house ICs), we build vertically integrated robotic systems in which software and hardware are tightly coupled.

• Imitation Learning
• Autonomous Robot Control
• Hardware-in-the-Loop

Current topics

• Low-latency bilateral control on FPGA that can be retrofitted to low-cost multi-joint arms (RSJ 2026)
• Accelerating motion generation of Vision-Language-Action (VLA) models by reusing the VLM's internal representation (RSJ 2026)
• Robot-arm motion generation with force-aware LLM in-context learning and dynamic movement primitives (RSJ 2026)
• Uncertainty-aware haptic shared control: teleoperated flexible-object manipulation with a humanoid robot (IEEE RA-L 2023)
• SNN-based imitation learning on a real robot (Scientific Reports 2026) and binary-neural-network-based flexible-object manipulation (IROS 2021)